The present disclosure herein relates to memory devices and methods of fabrication therefore and, more particularly, to multilayer memory devices and methods of fabrication therefor.
The degree of integration of semiconductor memory devices has continued to increase to meet user demands for superior performance and low price. In conventional planar (“two dimensional”) semiconductor memory devices, the degree of integration is generally determined by the area which a unit memory cell occupies. Therefore, integration of the device may be limited by the ability to form fine patterns. Producing finer patterns may require expensive production equipment.
“Three dimensional” (multilayer) memory devices including memory cells arranged in multiple layers have been proposed as a technique for increasing device density. However, mass production of such memory devices may require process technology that can realize a reliable quality of a product while reducing manufacturing cost per bit in comparison to conventional two dimensional semiconductor memory devices.